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[VHDL-FPGA-Verilog] pci144_vhdl

Description: PCI vhdl for Fpga designer to design PCI IP
Platform: | Size: 3072 | Author: 李晓媛 | Hits:

[VHDL-FPGA-Verilog] Pcit32vhdl

Description: PCI 32 target IP for Fpga/asic Designer
Platform: | Size: 428032 | Author: 李晓媛 | Hits:

[VHDL-FPGA-Verilog] pci_core

Description: pci CORES 从外国网站上弄下来的，大家可以看看啊-pci CORES from foreign web sites get down, we will look at ah
Platform: | Size: 28672 | Author: haitao | Hits:

[Embeded-SCM Develop] 9054

Description: PCI总线的高速数据采集卡设计资料（基于PCI9054 ）-PCI-bus high-speed data acquisition card design information (based on PCI9054)
Platform: | Size: 2058240 | Author: 斌 | Hits:

[Embeded-SCM Develop] PCI

Description: PCI总线系统结构、性能及总线操作时序和总线控制权的仲裁问题-PCI 脳 脺脧脽脧渭脥 鲁 陆 谩 鹿 鹿 隆 垄 脨脭脛脺 录 掳 脳 脺脧脽 虏 脵 脳 梅 脢 卤 脨貌 潞 脥 脳 脺脧脽 驴 脴脰脝脠 篓 渭脛脰脵 虏 脙脦脢脤芒
Platform: | Size: 138240 | Author: 顾鹏伟 | Hits:

[Embeded-SCM Develop] pci

Description: altera pci license al tera pci license -altera pci license al tera pci license
Platform: | Size: 1024 | Author: wang | Hits:

[VHDL-FPGA-Verilog] hgb_pci_host

Description: 内有一PCI 主 和PCI从，PCI TARGET 都是公开代码的，是工程文件，有仿真工程，使用说明。觉得好的就推荐一下。 本PCI_HOST目前支持： 1、 对目标PCI_T进行配置； 2、 对目标进行单周期读写； 3、 可以工作在33MHZ和66MHZ 4、 支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的！！！软件里面调试仿真了半天，终于调通了，到了下载就突然弹出窗口说包含了有限制的IP CORE，是限制使用的-There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of
Platform: | Size: 2712576 | Author: | Hits:

[VHDL-FPGA-Verilog] pcicard

Description: pci debug card 的VHDL源代码-pci debug card of the VHDL source code
Platform: | Size: 1024 | Author: wwww | Hits:

[VHDL-FPGA-Verilog] pci_core.tar

Description: vhdl 写的 PCI IP核程序，已经过测试-pci ip core
Platform: | Size: 23552 | Author: planet1997 | Hits:

[Embeded-SCM Develop] pcie_vera_tb_latest.tar

Description: FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number generation and checking • ACK TLP packets • Scrambling • MemRd MemWr CfgRd CfgWr TLPs -FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number generation and checking • ACK TLP packets • Scrambling • MemRd MemWr CfgRd CfgWr TLPs
Platform: | Size: 169984 | Author: Arun | Hits:

[VHDL-FPGA-Verilog] FPGA_8008

Description: pci pci转local bus总线的应用，使用IPcore alter器件-pci pci convert local bus application,use alter IP core
Platform: | Size: 493568 | Author: robincyh | Hits:

[VHDL-FPGA-Verilog] OpenCorespcicore

Description: PCI IP核功能实现，符合V2.2协议-realize pci function
Platform: | Size: 1203200 | Author: sophie | Hits:

[Software Engineering] pci

Description: pci总线设计在计算机多总线结构中，PCI总线以其速度高、可靠性强、成本低及兼容性好等性能，在各种总线标准中占主导地位，而基于PCI总线标准的接口设计己成为相关项目开发中的优先选择。现阶段PCI总线设计主要采用FPGA现场可编程逻辑阵列来设计，基于FPGA不但能大大缩减电路的体积，提高电路的稳定性，而且其先进的开发工具使整个系统的设计调试周期大大缩短，基于FPGA的PCI总线设计已经成为总线设计的最主要的设计方式。 本文提出了一种基于FPGA的PCI接口的简单设计方案，简要介绍了PCI总线的特点、信号、协议与命令，分析了时序设计要点，设计了一种基于FPGA的PCI总线的方案，写出了VHDL程序并进行仿真，仿真结果证明可以成功的进行总线的读写操作。 -pci bus design
Platform: | Size: 900096 | Author: 楠楠 | Hits:

[Embeded-SCM Develop] FPGA-PCI

Description: 基于FPGA的PCI接口源代码及Testbench Verilog程序代码-fpag pci
Platform: | Size: 467968 | Author: lang | Hits:

[USB develop] pci-verilog

Description: USB及PCI总线设计的一些源代码（经测试）-USB and PCI bus design some of the source code
Platform: | Size: 431104 | Author: tom | Hits:

[VHDL-FPGA-Verilog] opencore_crt

Description: 可以在Altera QuartusII下编译的Open Cores PCI桥源代码，是经过多天辛勤整理修改才完成的-Open Cores PCI bridge source code that can be compiled at Altera QuartusII. Modified under many days of hard work
Platform: | Size: 683008 | Author: Joe | Hits:

[SCM] PCI_express_layers

Description: PCI express layers doccuments
Platform: | Size: 397312 | Author: arsal | Hits:

[VHDL-FPGA-Verilog] sdram_pci

Description: 基于SDRAM的PCI采集程序，PCI9054控制器+SDRAM控制器Verilog源代码，，已经SignalTap调试通过。-SDRAM PCI-based acquisition program, PCI9054 Controller+ SDRAM controller Verilog source code, has SignalTap through debugging.
Platform: | Size: 3166208 | Author: wangbo | Hits:

[VHDL-FPGA-Verilog] pci_mini_latest.tar

Description: pci的代码，有利于关于PCI核的使用，帮助更多的人去学习-pci
Platform: | Size: 508928 | Author: yly | Hits:

[VHDL-FPGA-Verilog] pci

Description: pci总线源代码，总线设计参考。适合于飓风系列FPGA设计参考。-pci bus source code, the bus design. For hurricane series FPGA design.
Platform: | Size: 23552 | Author: Zeng.q | Hits:
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